Lalitha Gajula
Trainee Design Engineet at Analogport Pvt Ltd || Design Verification Trainee at Maven Silicon || Btech in RGUKT, Srikakulam - ECE\'23
- Role
- Trainee Design Engineer at Analog Port
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Lalitha Gajula
Hello there,I\'m Lalitha Gajula, graduated Btech from RGUKT - Srikakulam in the stream of Electronics and Communication engineering, and trained in Design and Verification course in Maven Silicon training institution, actively looking for an opportunity to Kickstart my VLSI Career as a Design Verification Engineer. I am looking forward to associate with an Organization, that can help me in enhancing my skills, strengthening my knowledge and realising my potential. I am willing to be a part of team that works dynamically towards the Objectives of the Organization and helps in its Growth.Technical Skills :HDL : VerilogHDVL : System VerilogEDA Tools : Ni Multisim, Modelsim, Quartus Prime, XilinxCoverage : Code Coverage, Functional CoverageOS : Linux, WindowsVerification Methodologies : System Verilog Assertions (SVA), Universal Verification Methodologies(UVM)
Experience
Trainee Design Engineer
Feb 2024 — Present · Bengaluru, IN
Education
RAJIV GANDHI UNIVERSITY OF KNOWLEDGE TECHNOLOGIES, SRIKAKULAM
Bachelor of Technology - BTech, Electrical, Electronics and Communications Engineering
RAJIV GANDHI UNIVERSITY OF KNOWLEDGE TECHNOLOGIES, SRIKAKULAM
Pre University Course, MPC
ZPP High School
SSC
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