Lalith Kumar Yadav Kornana
Senior Design Verification Engineer @Texas Instruments
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WORK HISTORY
Senior Design Verification Engineer @Texas Instruments
Bengaluru, IN
EDUCATION
Indian Institute of Technology, Madras
Master of Technology - MTech, Information security
Anil neerukonda institute of technology and sciences
Bachelor of Technology (B.Tech.), Electrical, Electronics and Communications Engineering
ABOUT LALITH KUMAR YADAV KORNANA
Had 6+ years of experience in RTL verification.Worked in SOC and IP DV domains.Worked on a Formal Verification for 3+ Years. Verified SoC modules and Mixed Signal IPs in Formal. Had a good experience in converging proofs using formal techniques. Planned scope of multiple Formal Applications (FPV, CSR, CONN) for SOC and IP DV areas.Worked on PCIe, Mixed signal Power/Reset/Clock Management module, ARM processors and Real-time control modules such as PWM etc,Worked on GLS verification and Coverage closureWorked closely with Design, Validation and Arch teams to discuss and improvise SoC aspects. Worked on customer problems and provided corresponding solutions on time.Protocols Known: PCIe, AXI, AHB, APB, UART, SPI protocols.Hands-on experience on System Verilog, UVM, C, C++, Perl and Python.
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