Lakshmi Narayana K

WORK HISTORY

EDUCATION

ABOUT LAKSHMI NARAYANA K

RTL design engineer with 12+ years of experience, skilled in RTL to GDSII flow of 4 major server soc tape-outs which includes following tasks : Micro-architecture from the specification, RTL coding using SV/Verilog/VHDL, Functional Simulation, Timing analysis, Timing fix in the RTL as well as in the netlist, CDC/RDC, Linting, Low power checks, and LEC between RTL, MAP, PRE, POST netlists. Strong protocol knowledge on UHS PHY, AXI, APB, ethernet, MIPI CSI and other high-speed serial protocols. Have strong hands on ECO\'s and synthesis and soc/ASIC integration and implementation. Worked extensively on 10nm technology designs.Languages : Verilog, VHDL and System Verilog, C.Standard protocols :(High speed custom bridges) USB2SATA, Ethernet, AMBA-AXI, APB, MIPI-PHY and UHS_PHY Scripting languages : PERL, TCLStandard simulators : Cadence NCSIM, Synopsys VCS, Mentor graphics Questa, RTL CompilerRevision controls : CVS, GIT ASIC/SOC : Conformal LEC, Design compiler Concepts : Digital Design, RTL Design, Micro architecture, FPGA, SOC/ASIC Integration. Front end checks : Lint, synthesis, Low power checks (UPF), CDC checks, Synthesis, Basic STA and LEC. FPGA : Xilinx,Altera and Lattice