Lakshman Vijrothu
Mts - Tlp Asic-cad Engineer @Micron Technology
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WORK HISTORY
Mts - Tlp Asic-cad Engineer @Micron Technology
Hyderabad, IN
Core Responsibilities-Design and optimization of simulation flows for SOC/IP projects-Development and support of LSF-based compute and license infrastructure-Creation of coverage flows to improve verification efficiency-Building and maintaining Jenkins CI/CD pipelines integrated with AI/ML for smart sanity testing and RCA-based flows-Management of Artifactory and Bitbucket flows for secure and scalable code delivery-Driving IP and SOC release flows for high-quality deliverables-Exploring and implementing AI/ML-based in-house solutions to enhance ASIC CAD workflows and automation-Evaluating and integrating vendor CAD/EDA tools to improve design flow efficiency and scalability.
EDUCATION
Jawaharlal Nehru Technological University Hyderabad (JNTUH)
Bachelor of Technology - BTech, ECE
BITS Pilani, Hyderabad Campus
Master of Technology - MTech, Microelectronics
Holy Angels Public School,Bhimavaram
High School, SSC
Government Institute Of Electronics
Special Diploma, Eelectronics
ABOUT LAKSHMAN VIJROTHU
Innovative ASIC CAD Engineer with extensive experience in developing and optimizing design flows for SOC/IP projects. Passionate about leveraging AI/ML to enhance CI/CD pipelines, improve coverage, and streamline release processes. Skilled in building robust infrastructure for simulation, licensing, and automation.Core Expertise:Simulation flows for SOC/IP projectsLSF-based compute and license infrastructure development and supportCoverage flows for verification efficiencyJenkins CI/CD pipelines integrated with AI/ML for smart sanity testing and RCA-based flowsArtifactory and Bitbucket flows for secure and scalable code deliveryIP and SOC release flows for high-quality deliverablesKey Innovations & Achievements:Invented Scalable Parallel Dependency Checkout Architecture for workspace optimizationImplemented dual-pipeline CI/CD with ML-based sanity testing, reducing compute and license overheadDeveloped AI/ML-driven RCA flows for faster issue resolutionEnhanced coverage and simulation flows for improved verification metricsCareer Highlights:Principal ASIC CAD Engineer-II, Micron Technology – Led Hyderabad ASIC CAD team; responsible for SOC/IP verification tools, infrastructure, automation, workspace management, version control flows, EDA tool evaluations, and Jenkins CI/CD powered by AI/MLMember Technical Staff, AMD – SOC design automation methodologies and flowsSenior CAD Engineer, Lattice Semiconductor – Site CAD/EDA activities for digital and analog toolsSr. Design Engineer, AMD CV/VMT Team – Developed SOC/IP tool alignment automation, Perforce wrappers, vendor tool qualification, RTL delivery flowsFront-end CAD Engineer, Qualcomm – Autoreg and Autoseq development for register/configuration automationConsultant, AMD (Magna Infotech) – Global Build Flow developer for parallel-safe simulation buildsConsultant, Cadence – FPGA system planner validation for Xilinx and Altera architecturesAssociate MTS, Taray – Verification and validation of Memory Interface Generator for Xilinx FPGAsSkills: ASIC CAD, Simulation Flows, CI/CD Automation, AI/ML in EDA, Jenkins, LSF, License Management, RCA Analysis, Artifactory, Bitbucket, SOC/IP Release Management.
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