Lakshmanan Kannappan
Senior Formal Verification Engineer @NVIDIA
Austin, TX, US
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+91 *********19
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WORK HISTORY
Aug 2018 — Present
Senior Formal Verification Engineer @NVIDIA
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Austin, TX, US
Austin, Texas Area
EDUCATION
2008 — 2010
University of Florida
Master of Science
ABOUT LAKSHMANAN KANNAPPAN
Technically accomplished professional with over 8 years of experience in ASIC Design/Verification for Snapdragon family ARM CPU power subsystem using Verilog, System Verilog, Formal Verification and UVM methodologies.Specialties: Formal Verification (developing cycle accurate golden models using System Verilog and writing SVA\'s), UVM scoreboard developmentLanguages/Methodology:Verilog, System Verilog, UVM
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