Lakshmana Kamatham
Senior Member of Technical Staff Engineer at AMD, Hyderabad | MIEEE | Semiconductor Verification Engineer | Manager at AMD | Building skills in chip design
- Role
- Senior Design Verification Engineer at 意法半導體
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Lakshmana Kamatham
Processor verification•Strong knowledge in Processor/Computer architecture.•Worked on Testbench development using Systemverilog.•Experience in creating Testplans as per micro-architecture spec.•Strong background in Digital Logic Design and Verification.•Writing Functional coverage and analyzing Functional/Code coverage.•Writing Assertions and Testcases using assembly/system Verilog.•Debugging skills using Verdi and NSim tools.•Familiar with Systemverilog, Verilog, C, C++, Assembly, PERL
Experience
Senior Design Verification Engineer
Mar 2020 — Present · SG
Education
Acharya Nagarjuna University
B-Tech, Electronics & Communication Engineering
2007 — 2011
Nagarjuna University, Andhra Pradesh
B.Tech (E.C.E)
the Board of Secondary Education, Andhra Pradesh
High School
2004 — 2005
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