Lahar Baruah
M.Tech VLSI 2025 | Seeking opportunities in RTL, Design Verification | Verilog, SystemVerilog, UVM | APB, AXI, AHB
- Role
- Design Verification Trainee at Logic Cells Technologies
- Location
- Guwahati, AS, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Design Verification Trainee
Aug 2025 — Present
Education
Indian Institute of Information Technology Guwahati
Master of Technology - MTech, VLSI and Embedded Systems
Tezpur University
Bachelor of Technology - BTech, Electronics and Communication Engineering
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