Kiran Valkeshwar Patil
ASIC Designer | Cadence | Ex-Rambus
- Role
- Principal Engineer at Cadence
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Kiran Valkeshwar Patil
Core Competancy: Comprehensive knowledge of ASIC Flow,Good knowledge and experience…
Experience
Principal Engineer
Aug 2024 — Present · IN
Education
Savitribai Phule Pune University
Bachelor of Engineering (B.E.)
2008 — 2012
Yashwantrao Chavan College Of Enginnering an Autonomus Institute affilated to Nagpur University
Master of Technology (MTech)
2013 — 2015
Skills
- Cmos
- Floorplanning
- Tanner Eda
- Matlab
- Low-Power Design
- Signal Integrity
- Dft
- Shell Scripting
- Asic Flow
- Lvs
- Static Timing Analysis
- Microsoft Excel
- Ruby
- Clock Tree Synthesis
- Html
- Timing Closure
- C
- Physical Design
- Synopsys Primetime
- Linux
- Place & Route
- Synopsys Dc Compiler
- Verilog
- Drc
- Digital Logic Design
- Ic Compiler
- Physical Verification
- Perl
- Eda
- Design for Manufacturing
- Tcl
- Sysnopsys Custom Designer
- Microsoft Office
- Vlsi
- Logic Design
- Unix
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