Kushal Sreedhar

About Kushal Sreedhar

Integrated Circuits• VLSI design: Circuit Schematic entry and Layout of gates, flip-flop, Opamp, DAC, SAR-ADC, Decoder, SRAM cell, array and associated WR/RD circuitry, Ripple-carry Adder• Verilog code and test bench for basic gates, buffer, adders, counters, SAR• Skilled Knowledge of Analog and digital oscilloscopes, function generators, synthesizer, logic analyzers, multimeter, NI Data Acquisition unitDigital Systems Test• Credence Sapphire with ETC thermal solution setup (SRAM Array Debug and characterization)• ATE Test program and Memory BIST engine (DUT)• Array Test (Controllers, JTAG etc) including hardware and softwareProgramming• Basics of C and C++, Perl Scripting• RTL behavioral description (FSM Modeling) for digital systems: Verilog and VHDL• Assembly Language (x86)Specialties: Tools• MATLAB, Xilinx ISE 9.1, ModelSim, Code Composer Studio v4, Keil µVision3, SUPREM, NGEDA• Cadence tools: OrCAD 9.1-Capture CIS and PCB Layout Editor; Virtuoso, Assura, Spectre, HSpice, LTSpiceOperating systems• Windows (9x/XP/7), Unix (Ubuntu, Red Hat)

Experience

1. Principal Engineer

   Intel

   May 2025 — Present · Portland, OR, US

   Process-Design Technologist leading Technology readiness, Pathfinding, DTCO and Product development of Next-Gen Intel Client CPU.

Education

• RNS Institute of Technology

  BE, Electronics and Communication

  2006 — 2010

• Georgia Institute of Technology

  MS, Electrical and Computer Engineering

  2010 — 2012

Skills

• Circuit Design
• Modelsim
• Virtuoso
• Redhat
• Vlsi
• Orcad
• Matlab
• Ltspice
• Vhdl
• Analog
• Verilog
• Xilinx
• Cadence
• Cadence Virtuoso
• Spice
• Computer Architecture
• Spectre
• Fpga
• Integrated Circuit Design