Kushal R. Shah

Physical Design Engineer at Intel Corporation

Role
Physical Design Engineer at Intel
Location
Hillsboro, OR, US
LinkedIn followers
500 followers

About Kushal R. Shah

Physical Design Engineer with 7+ years of experience working in the semiconductors industry. Skilled in Application-Specific Integrated Circuits (ASIC) flow includes Synthesis, Place & Route, Power Analysis, Optimization, and SystemVerilog. Strong engineering professional with a Master of Science (M.S.) focused on Electrical and Computer engineering from Portland State University, Oregon.

Experience

  1. Physical Design Engineer

    Intel

    Mar 2019 — Present · Hillsboro, OR, US

    Member of Block level Power, Performance, Area analysis (PPA) and Co-optimization team for Intel advanced technology nodes.• Design Bring-up on Synthesis/APR/Signoff flows.• PPA studies for advanced node technology definition using flavors of technology collaterals and co-optimization (DTCO).• Lead TFM enablement for multiple projects/blocks.(Enable PPA friendly vendor based Reference Flow/ production based flow and share optimized TFM recipes to design partners - Shift left through DTCO efforts)• Advanced Analysis Metrics construction using Standard EDA tools and Tcl and partner with SWI team for infrastructure improvements. • Ramp up / Mentor new team members and co-lead organization wide Learning Academy for new hires.

Education

  • Portland State University

    Master of Science (M.S.), Electrical and computer engineering

    2016 — 2018

  • L.D. College of Engineering

    Bachelors of engineering, Electronics and communication

    2012 — 2016

Skills

  • Power Analysis
  • Static Timing Analysis
  • C
  • Programming
  • Synopsys Primetime
  • Cadence Innovus
  • Design Rule Checking (Drc)
  • Python
  • Place & Route
  • Java
  • C
  • Systemverilog
  • Application-Specific Integrated Circuits (Asic)
  • Ic Compiler
  • Upf
  • Floorplanning
  • Tcl
  • Field-Programmable Gate Arrays (Fpga)
  • Parasitic Extraction(Pex)
  • Cadence Virtuoso
  • Verilog
  • Microsoft Office
  • Vlsi
  • Primetime Ptpx
  • Teamwork
  • Synopsys Dc Compiler
  • C++
  • Layout Versus Schematic (Lvs)
  • Logic Synthesis
  • Social Media
  • Very-Large-Scale Integration (Vlsi)
  • Management
  • Matlab
  • Low-Power Design
  • Microsoft Word

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Kushal R. Shah — Physical Design Engineer at Intel in Hillsboro, OR, US | Unifers