Kunj Rana
- Role
- Design Engineer at Intel
- Location
- Bengaluru, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Kunj Rana
RTL/ASIC design engineer with 5 years+ of experience in core IP development. Skilled in…
Experience
Design Engineer
May 2018 — Present
Skills
- Modelsim
- Integrated Circuit Design
- Vlsi
- Matlab
- Verilog
- Xilinx
- Asic
- Digital Signal Processors
- Physical Design
- Digital Design
- Tcl
- Systemverilog
- Rtl Design
- Cadence Virtuoso
- Perl
- Fpga
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