Kunal Bansal
- Role
- Senior Design Verification Engineer at Apple
- Location
- Redmond, WA, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Kunal Bansal
FPGA IP development and verification experience ~3 years: RTL/design/DV, E2E…
Experience
Senior Design Verification Engineer
Apr 2023 — Present
Skills
- Algorithms
- Verilog
- Modelsim
- Vhdl
- C++
- Vlsi
- Asic
- Embedded Systems
- Javascript
- Microcontrollers
- Debugging
- Verilog Hdl
- Pspice
- Computer Architecture
- C
- Cadence Virtuoso Layout Editor
- Cadence Spectre
- Struts
- Java
- Cadence Virtuoso
- Perl
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