Kunal Desai

About Kunal Desai

Specialties: RTL/uArch Design from scratch, uArch Innovation for Perf-Power-Area optimization, LPDDRx Memory Systems, Memory Controller and PHY, AXI/AHB SoC interconnects, NoC, DDR sub-system clocking and timing, SoC Architecture, High Speed Mixed Signal PHYs, CDR

Experience

1. Director of Engineering

   Qualcomm

   Sep 2011 — Present · Bengaluru, IN

   Complete uArch ownership/innovation in DDR Memory Controller and SoC Interconnect End to End ownership from uArch/Arch -> Design/RTL -> Synth/Timing to surpass all PPA GoalsAwarded \" Innovator of the Year\" for 2019Proven Innovator with multiple Granted and pending PatentsMentoring a large diverse team uArch/Design/RTL/DV/Synth/TimingLPDDRx Memory controller and sub-system design, timing, architecture, area/power optimization High speed AXI/AHB interconnect design.Digital signal processing : FIR/IIR filter design from scratch;Network on chip (Arteris) InterconnectMulti-site team work experience. Primary interface of the team with international teams

Education

• Indian Institute of Science (IISc)

  M. Tech, VLSI

  2004 — 2006

• D. J. Sanghvi College, Mumbai

  B. E., Electronics & Telecom

  2000 — 2004

• University of Mumbai

  B.E., Telecom

  2000 — 2004

Skills

• Mixed Signal
• Static Timing Analysis
• Vlsi
• System on a Chip (Soc)
• Rtl Design
• Timing Closure
• Logic Design
• Field-Programmable Gate Arrays (Fpga)
• Verilog
• Debugging
• Application-Specific Integrated Circuits (Asic)
• Fpga
• Very-Large-Scale Integration (Vlsi)