Kumar Avala
Principal Application Engineer at ANSYS, Inc
- Role
- Principal Engineer at Ansys
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
About Kumar Avala
20 years of Experience in VLSI & Electronic Design Automation domain.• Experience in Power Noise and Reliability analysis that includes IR drop analysis, Power/Signal EM, ESD analysis, Substrate analysis etc.• Responsible for growing ANSYS business by engaging in pre and post-Sales technical engagements with ANSYS/Apache customers.• Involve mostly customer on-site engagements, involve in customer projects and work with them for successful deployment of ANSYS tools on customer projects.• Involve in product evaluations, bench-marking using ANSYS tools to win new business.• Provide technology/tool trainings to customers and provide post sale support for ANSYS tools(RedHawk and Totem) with extended help from ANSYS RnD.• Understand and review Design implementation, suggest and implement methods for improved QoR and design closure run-times.• Customer tool flow assessment, understanding of Technology Design kits, suggest methods and work for optimal usage of ANSYS tools in the customer environment.
Experience
Principal Engineer
Apr 2021 — Present · San Jose, CA, US
Work with R&D and Product Engineering Teams to address product defects and develop new flows to meet customer requirements• Conduct technical presentations and product demonstrations to customers.• Support technical evaluations/benchmarks and drive the process to deliver ANSYS solutions implementations• Assists sales staff in assessing potential application of company product to meet customer needs and applying the tools and flows.• Participate in customer benchmark and pre-release activities• Develop strong, positive customer support• Instruct and Train customers on how to produce optimal quantitative and qualitative results using Ansys EDA tools
Education
JNTU Anantapur
Bachelor of Technology (B.Tech.), Electronics and Communications Engineering
1997 — 2001
Skills
- Power Analysis
- Static Timing Analysis
- Debugging
- Physical Design
- Asic
- Physical Verification
- Primetime
- Tcl
- Timing Closure
- Semiconductors
- Soc
- Vlsi
- Low-Power Design
- Eda
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.