Kumar Siddhant
Senior Design Verification Engineer
- Role
- Senior Design Verification Engineer at Mirafra Technologies
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Kumar Siddhant
Programming Languages: C, Python and Verilog. Areas of interest: Digital IC Design, Memory Design, Physical Design, STA, Analog/RFIC Design, Low Power Design. Tools: Xilinx ISE, Xilinx Vivado, Cadence Virtuoso, FPGA, MATLAB Simulink.
Experience
Senior Design Verification Engineer
Sep 2024 — Present · Hyderabad, IN
Education
RIMT- Institute of Engg. and Technology, Mandi Gobindgarh
Bachelor of Technology - BTech, Electronics and Communications Engineering
2012 — 2016
Indian Institute Of Information Technology Allahabad
Master of Technology - MTech, Microelectronics,VLSI
2018 — 2020
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