Kumar Rajeev R.

About Kumar Rajeev R.

Experienced Design verification engineer with track record of \"Zero Defect IP/SubSystem/SoC DV with multiple first pass silicons\" Team player, leader and mentor medium sized team(10-15 members). Complete ownership of IP/SubSystem/SoC verification, TB Architecture and development from scratch, Checks(Verilog based or SVA), Functional and Code Coverage Closure, Project tracking and completion, Technical support to customers, VIP/simulator vendor engagement and issues tracking.PROJECT EXECUTION- Project planning and execution - Resource planning - Micro-Architecture to system level scenarios identification - Risk analysis and mitigation planVERIFICATION EXPERTISE - Testbench Architecture [Simulation based( RTL,GATE level, Functional Safety & Memory)- Verification Plan, Coverage Metrics development- IP/sub-system/SoC Verification- Gate level simulation- Low Power Verification- Debug( ARM Coresight) architecture - Security(ARM TrustZone) verification- Bootcode Verification- Multi-core SoC verification- Coverage Closure PROTOCOL EXPERTISE- Architecture : ARM Cortex-M- Connectivity : WiFi, Bluetooth/BLE- Serial Peripheral : I2C, I2S, SPI, UART, SMBus, MIPI I3C SenseWire- Camera & Display : MIPI-CSI2, MIPI-DPHY, MIPI-CPHY- Memory : LPDDR5, GDDR6, DFI, NOR/NAND QSPI Flash memory[MICRON/ CYPRESS/ WINBOND/ GIGADEVICE]- ISO-26262 Safety compliant IP Verification [Camera & Display IPs]- Crypto IPs/Algorithms: AES, Poly1305 Chacha20, SHA- USB-2.0, DataWire, SDIO, AHB/APBMETHODOLOGY EXPERTISE- UVM, OVMSIMULATOR- VCS, Questa, XceliumDEBUGGING TOOL- Synopsys - DVE, VERDI- Cadence - SimVision- Mentor - qvsim, VisualizerSCRIPTING- Shell Scripting (csh, bsh)- Python• Familiar with gate level simulation.• Familiar with boot rom simulations (Multi-Cores)• Familiar with FPGA emulation.

Experience

1. Principal Engineer

   Infineon Technologies

   Sep 2021 — Present · Bengaluru, IN

   Exploring a new vertical of Premium Quality Automotive, IoT, High Performance Computing and Wireless Products.Led ~25 members SoC DV team and delivered \"First Pass Silicon\". Milestone towards Infineon success.

Education

• Guru Gobind Singh Indraprastha University

  B. Tech, ELECTRONICS AND COMMUNICATION ENGINEERING

  2006 — 2010

Skills

• Simulation
• Coverage Analysis
• Rtl Coding
• Sata 3.0
• C
• Vlsi
• Systemverilog
• Questa
• Protocol Analyzer
• Functional Verification
• Ncsim
• I2c
• Spi
• Semiconductors
• Open Verification Methodology
• Arduino
• Universal Verification Methodology (Uvm)
• Soc
• Asic
• Design and Verification
• Perl
• Eda
• I2s
• Verilog
• Rtl Design
• Vcs
• Drone
• Vmm
• Cloud Applications
• Uvm
• Dve
• Very-Large-Scale Integration (Vlsi)
• Vhdl
• Simulations
• C++
• System on a Chip (Soc)
• Application-Specific Integrated Circuits (Asic)
• Static Timing Analysis
• Debugging
• Linux