Kumar Nandan

About Kumar Nandan

As a Senior Principal Design Engineer at Cadence with extensive experience in PCIe/CXL controller development, and contribute to IP architecture, RTL development including Lint, CDC and Synthesis processes. With over a decade of experience in SoC design and implementation, my work is driven by a commitment to technical excellence and collaboration. My expertise encompasses front-end design, RTL integration, constraints modifications, and synthesis flows, enabling me to support cross-functional teams and projects effectively.Expertise : RTL integration, PCIe + Ethernet lead. Hands on knowledge in Fusion Synthesis, RM FC Flow development. SOC Integration, Constraints, RTL Quality, FEBE Tech Lead. FE Implementation checklist Signoff lead. Synopsys design flow : VCS, Formality, Spyglass Lint, SDC and CDC. Hands-on experience on PT constraints consistency (PTC) and STA reports evaluation. Proficient in LINT, RDC, CDC, timing checks, FC sanity checks evaluation Supported customer engagements by providing technical expertise + addressing design query. Ability to work effectively in cross-functional teams and communicate technical concepts clearly. CoE Technical Lead [5yr] & Managed Tech-Mahindra, Mirafra, Sevitek.[20••••25] Synopsys : SS delivery for PCIE+Ethernet Projects. INTEL : Server, HBM, IP lead for PCIE Gen4/5/6. Qualcomm Snapdragon Chips Broadcom : Routers, TCAM SanDisk : NAND memory[Synopsys] RTL Integration, Constraints updates, Led PCIe + Ethernet activities Fusion Compiler Synthesis Setup & Leading Fusion Synthesis Flow. FE implementation processes. perform floor planning, timing constraints. Formality R2R + R2G RM FC Flow design, timing closure for PCIe/Ethernet.[INTEL] RTL Integration lead for SOC projects Fusion compiler Synthesis flow/LEC/Caliber/STA), CDC, Fishtail. RTL checks and flows to maintain the health of SOC Design to deliver BE Team for Synthesis. Expertise in delivering FE collaterals + Synthesis delivery DC/FC Fusion compiler Synthesis, Caliber, Fishtail. EFFM Emulation design flow[QCM, BRCM] PCIE verification wrt Server projects, Networking chips Strong hands on experience NAND memories, SATA, PCIe, Coverage and Emulation GLS, Vectors, Code/Functional coverage, SDF & Timing Debug. Super macro verification for Router projects in BROADCOM. BROADCOM : Functional, ESPCV verification for TCAM, SCAN.Education: CDAC RND VLSI design Pune :95.99%tile, AIR 21B.E in ECE : LNCT- 82.96% 1st rank in RGPV, Bhopal.Passion about Photography ~7yrs

Experience

1. Senior Principal Design Engineer

   Cadence

   Jan 2026 — Present · Bengaluru, IN

   PCIe/CXL Controller Development : IP Architecture [ RTL Design, Synthesis ]

Education

• Indian Institute of Management, Kozhikode

  Executive Management Development Program, Advanced Product Management

  2021

• Ram Krishna (R.K.) College, Madhubani

  Intermediate in Science , PCM

  1995 — 2007

• Rajiv Gandhi Prodyogiki Vishwavidyalaya

  Bachelor of Engineering (B.E.), Electronics and Communications Engineering

  2007 — 2011

• Centre for Development of Advanced Computing (CDAC-ACTS) Pune HeadQuarter

  P.G. in VLSI, VLSI DESIGN - July 2011 - Jan 2012

  2011 — 2012

Skills

• Fpga
• Asic
• Universal Verification Methodology (Uvm)
• Flash Memory
• Circuit Design
• Uvm
• Logic Synthesis
• Vmm
• System Verilog Assertion
• Verification
• Ncsim
• Vhdl
• Simulations
• Application-Specific Integrated Circuits (Asic)
• Logic Design
• Static Timing Analysis
• Digital Electronics
• Hardware Description Language
• Synopsys Tools
• Rtl Verification
• Assertion Based Verification
• Integrated Circuit Design
• Sva
• Linux
• Modelsim
• Vlsi
• Functional Verification
• Rtl Design, Synthesis
• Ic
• System on a Chip (Soc)
• Verilog
• Rtl Design
• Field-Programmable Gate Arrays (Fpga)
• Amba Ahb
• Rtl Coding
• Cmos
• Javascript
• Open Verification Methodology
• C
• Soc