Kumar Buddavarapu
Senior RTL Design Engineer at AMD(Client) |Ex-UTSian-Unistring Tech Solutions Pvt. Ltd. (UTS)FPGA | RTL | VLSI | CDC | STA | VHDL | VERILOG | ZYNQ | Vivado | ModelSim | Synthesis | Implement |
- Role
- Senior Rtl Design Engineer at TEKsystems
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Kumar Buddavarapu
Experienced FPGA and RTL Design Engineer with a successful track record of Three (3) years, specializing in VHDL coding and its application in defense-related projects to enhance warfare capabilities for the Indian defense sector. Proficient in designing and implementing innovative solutions to address complex challenges. Skilled in collaborating with multidisciplinary teams, analyzing requirements, and delivering high-quality results within tight deadlines. Committed to leveraging my technical expertise and passion for defense technologies to drive advancements and contribute to the growth and success of defense-oriented organizations.
Experience
Senior Rtl Design Engineer
Oct 2024 — Present · Hyderabad, IN
Education
BITS Pilani Work Integrated Learning Programmes
Master's degree, Microelectronics
Lakireddy Bali Reddy College of Engineering(Autonomous)
Bachelor of Technology - BTech, Electrical, Electronics and Communications Engineering
Sri Venkateswara University
Diploma, Biomedical/Medical Engineering
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.