Eduardo Corpeño

Silicon Engineering Specialist @埃森哲

Ottawa, ON, CA

Validate functionality, performance, and robustness of silicon designs prior to tape-out by developing and executing test plans, building verification environments, and implementing testbenches in SystemVerilog and UVM. • Debug RTL and gate-level simulations, analyze functional coverage, and work closely with design and architecture teams to ensure correctness across complex SoCs and subsystems.• Ensure RTL quality and consistency through automated static analysis flows including Lint, CDC, RDC, and elaboration checks. • Develop and maintain rule sets aligned with project standards, debug and classify violations, and collaborate with design teams to improve RTL hygiene and signoff readiness. • Maintain rule-checking infrastructure as designs evolve.• Write computer code to maintain scripts, tools, and infrastructure to streamline DV and RTL rule-check workflows. • Automate regressions, build systems, and job orchestration using Python, C++, Java, Shell, Makefiles, and CI tooling.• Manage source control and task tracking via Git, Perforce, and Jira. • Build dashboards, monitor nightly regressions, and support efficient developer workflows across Linux-based environments.

Universidad Francisco Marroquín

BS, Electrical and Computer Engineering

Georgia Institute of Technology

Master of Science (MSc), Computer Science