Kanwaldeep Sobti

About Kanwaldeep Sobti

Over 17 years of progressive semiconductor product development experience, in senior engineering manager, manager, project lead & individual contributor roles• New product development and execution - proven track record of successful execution including first pass silicon successes• Extensive project management experience - indicator driven execution focused on delivering high quality SoCs on time• Extensive global stakeholder management experience. Multiple times successfully led a multi-domain, multi-cultural and multi-site team to successful project execution• Deep understanding of all aspects of IP/SoC design methodology and design phases from feature definition, RTL design and verification, test, and ramp to production.• Experience in growing and leading large SoC teams, nurturing technical leadership, including building teams from the scratch

Experience

1. Engineering Manager

   Intel

   Aug 2018 — Present · Bengaluru, IN

   Managing and leading the multi-geo matrixed engineering team, responsible for overall functional verification sign-off at MCP level for upcoming chiplet based Xeon server SoCs. o Key responsibilities include defining overall verification strategy across simulation and emulation platforms; defining various project phases/milestones; scoping the deliverables; aligning the stakeholders across emulation, firmware, chiplet design and verification teams; defining design review process etc. • Additionally, managed a team of design verification and integration engineers and successfully delivered multiple hardened sub-systems of path-breaking high-speed IO technologies (PCIE Gen5/CXL) and data acceleration technologies, implemented in Intel7 technology, that enabled 6+ server SoCs (developed for datacentre, HPC and edge server markets). o Responsible for all aspects of IP integration; SoC level fabric design; RTL static quality tools sign off; verification of all functional features and chip pervasive logic such as reset, clocking, complex power management flows, security logic, RAS features, DFx; performance verification etc.

Education

• Arizona State University

  MS, Electrical Engineering

  2005 — 2007

• Delhi College of Engineering

  B.Tech, Electronics and Communications engineering

  1998 — 2002

Skills

• Verilog
• Vlsi
• Soc
• Rtl Design
• Microprocessors
• Asic
• Debugging
• Static Timing Analysis
• Functional Verification
• Tcl
• Eda
• Semiconductors
• Processors
• Vhdl
• Perl
• Low-Power Design
• Logic Design
• Dft
• Timing Closure
• Systemverilog
• Ic
• Integrated Circuits (Ic)