Kshitij Kulshreshtha

About Kshitij Kulshreshtha

Almost 18 Years of experience as VLSI design engineer with good knowledge in a range of…

Experience

1. Principal Design Engineer

   新思科技股份有限公司

   Apr 2024 — Present

Education

• RMIT University

  Microelectronics Engineering

• RMIT University

  Master of Science (MS)

Skills

•  Improvement of the Design Testability
• Eda
• Macro Structure and Boundary Scan Verification
•  Mbist Insertion and Design Verification
•  Scan Insertion and the Related Issues
•  Atpg Vectors Generation and Verification
• Test Structures Verification
• Verilog
• Automation by Building Different Gui Scripts to Reduce Tat During Test Insertion
• Ic
• Dft
• Test Coverage Improvement
• Fixing the Dft Violations in Accordance with Dft Checks
• Improvement of Testability Logic
• Vlsi
• No Timing and Timing Patterns Simulation
• . Involved in the Generation of Different Test Rules for Example; Scan
• . Formal Verification
• . at-Speed Structural Testing
• Test Patterns Generation and Patterns Simulation
• Testing