Kshitij Dutta
Design Verification Intern @Coverify
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WORK HISTORY
Design Verification Intern @Coverify
Gurugram, IN
Utilizing the Embedded UVM (eUVM) framework for processor verification, developing layered testbenches in D programming language using a Verilator-based simulation flow. Worked on projects involving Avalon-MM interface and SHA3 testbenches, focusing on constraint-based input randomization, injecting edge cases, and analyzing DUT behavior through waveform debugging using GTKWave. Gained hands-on experience with simulation environments and toolchain management, including Makefile-based builds, LDC2 linking, and managing execution flow across SV and D environments.
EDUCATION
Delhi Technological University (Formerly DCE)
Bachelor of Technology - BTech
ABOUT KSHITIJ DUTTA
Student at Delhi Technological University
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