Sai Harish K.
ASIC Engineer | RTL Design
- Role
- Design Engineer at Cadence
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Sai Harish K.
ASIC Engineer. RTL Design - PCIe MSI-X, DoE, IDE. SoC Integration - PCIe, LTPI, SPI/QSPI. SoC Verification - PCIe, SPI/QSPI, eSPI, LTPI, I2C, IPC, gDMA.Silicon Bringup - PCIe, SPI/QSPI with various Flash models, Oscilloscope and Logic Analyzers.
Experience
Design Engineer
Dec 2025 — Present · Bengaluru, IN
SSG, PCIe Controller Design
Education
BITS Pilani Work Integrated Learning Programmes
Master of Technology (M.Tech), Microelectronics
Velagapudi Ramakrishna Siddhartha Engineering College
Bachelor of Technology (B.Tech.)
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