Krushnakant Pawar
Digital Design Engineer (Cisco) | M.Tech (IISc) | B.Tech (COEP)
- Role
- Senior Asic Engineer at Cisco
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Krushnakant Pawar
I\'ve been involved with Cisco\'s cutting-edge SiliconOne device family, focusing on RTL design and verification for intricate blocks spanning various clock domains.
Experience
Senior Asic Engineer
Sep 2023 — Present · Bengaluru, IN
Education
COEP Technological University
Bachelor's Degree, Electronics and Telecommunications Engineering
2012 — 2016
Indian Institute of Science (IISc)
Master of Technology - MTech, Electronic Systems Engineering (Formerly CEDT)
2018 — 2020
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