Krishnendhu U. N
RTL Design Engineer
- Role
- Asic Design Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Krishnendhu U. N
Experience Summary:• Overall experience of 6+ Years in FPGA RTL Design, Integration and Testing,ASIC RTL signoff and software• Working as Senior Design Engineer for Cerium Systems. Client -Intel (From August 2020 to till date)• Worked as Senior Design Engineer for Cerium Systems. Client – Cisco Systems (From April 2018 to July 2020).• Worked as Design Engineer in Park Controls and Communications from December 2015 to March 2018.Technical Skills:• FPGA: Artix-7, Cyclone-IV, Cyclone-V,Microsemi Smartfusion• Microsemi Libero, Xilinx Vivado, Synplify pro, Altera Quartus 16, Qsys, Signal tap logic analyzer, SOPC Builder, ModelSim,Synopsis DVE,Spyglass Lint,Spyglass CDC, Design compiler, Fusion compiler, LEC,ATPG and Caliber.• HDL Languages: VHDL, Verilog, RDL (Register descriptive language) • Software Languages: C (basic) and C++• Protocol : Ethernet MAC, SGMII, MII, RMII,UART, SPI, I2C, MDIO Clause-22, MDIO Clause-45
Experience
Asic Design Engineer
Aug 2019 — Present
On Contract
Education
Cochin University of Science and Technology
Bachelor of Technology - BTech, Electrical, Electronics and Communications Engineering
2009 — 2013
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