Krishnamachary Prathapuram

About Krishnamachary Prathapuram

Demonstrated over 25+ years of comprehensive expertise in diverse ASIC/SOC domains including Physical Design, STA, DFT, Design, and Verification- Led and managed a high-performing team of 40+ Engineers, fostering collaboration and achieving project milestones- Engaged in the successful Tapeout/Execution of 40+ SOC/ASIC projects spanning technology nodes from 180nm to cutting-edge 3nm- Specialised in steering complex chip Physical Design activities, ensuring precision and optimal outcomes- Proficiency in developing and implementing Timing Constraints for various modes, executing STA planning, and achieving Sign-Off for intricate SOCs, handling complexities in clocks, modes, Timing corners, and size- Extensive experience in overseeing full SOC/ASIC projects, displaying in-depth understanding and execution of Fullchip Floorplan/Bus/Feedthru, STA Planning/Execution/Sign-off, Physical Design Closure of Critical Blocks, DFT Architecture, and Constraints Development for STA, IR/EM Analysis using RHSC, Post Silicon ATPG debug, Formal verification, Block Design, and Verification- Successfully led Fullchip timing closure for more than 20 ASIC/SOCs comprising 200+ million gate SOCs- Pioneered the development of methodologies, automation tools, and productivity enhancement techniques, ensuring efficient project execution and progress tracking.

Experience

1. Asic Director

   Juniper Networks

   Jul 2022 — Present · Bengaluru, IN

Education

• Kakatiya University

  Bachelor of Science , Instrumentation

  1995 — 1998

• National Institute of Technology Warangal

  M.Sc.Tech, Engineering Physics with Specialization in Photonics(Electronics & Optical communications)

  1998 — 2001

Skills

• Clock Tree Synthesis
• Testkompress
• Fullchip Dft Architecture
• Dft Compiler
• Spyglass Predictive Analyzer
• Static Timing Analysis
• Physical Design
• Timing Closure
• Silicon
• Perl
• Eda
• Good Understanding of Physical Verification ( Lvs , Drc) Sign-Off
• Logic Synthesis
• Primetimesi
• Synthesis
• Vhdl
• Shell
• Dft
• Functional Verification
• Primetime
• Ir Drop
• Verification
• Tcl
• Asic
• Rtl Design
• Nanotime
• System on a Chip (Soc)
• Conformal Lec
• Pnr
• Verilog
• C++
• Fastscan
• Sta
• Rtl Coding
• Floorplanning
• Block Level Rtl Design
• C
• Soc
• Vhdl , Verilog
• Vlsi