Krishna Parshurampuriya

About Krishna Parshurampuriya

Myself Krishna is having ~14 years of experience in STA.I am having experience in Timing closure for Chiptop level/ SubSystem level. I have worked on 3nm-28nm design for prelayout to post-layout timing signoff.Mine responsibility includes all timing signoff checks like constraint_check/setup/hold/interface/DRC checks.My latest role on ongoing project - Timing Signoff for 36M Subsystem with 4lpe. Ensure All the macro level constraints should pass at Subsystem level and Chiptop level. Ensure the Chip should be timing clean in multiple modes and corners. Give feedback to individual block\'s layout owners to fix violations if required at Sbsystem/SOC level Review all unconstrained Endpoints present whether they are ok or not. Give feedback to layout to fix violations and suggest how these violations can be fixed. Generate ECOs for interface violations at later stage.

Experience

1. Staff Engineer

   高通

   Dec 2023 — Present · San Diego, CA, US

Education

• Sikkim Manipal Institute of Technology - SMU

  Bachelor of Technology (B.Tech.), Electronics and Communications Engineering

  2007 — 2011

Skills

• Scan Insertion
• Timing
• Drc
• Tcl-Tk
• Application-Specific Integrated Circuits (Asic)
• Physical Design
• Dft
• Perl
• System on a Chip (Soc)
• Place & Route
• Timing Closure
• Scripting
• Semiconductors
• Verilog
• Soc
• Primetime
• Shell Scripting
• Perl Script
• Asic
• Design Rule Checking (Drc)
• Low Power Synthesis
• Static Timing Analysis
• Digital Electronics
• Logic Synthesis