Kranthi Rajoli

About Kranthi Rajoli

ASIC physical design engineer with experience working on multi-million gate networking ASICs. Worked in various roles covering the entire spectrum of the ASIC physical design flow. Starting from Synthesis, Place & Route, timing closure/STA to physical verification and signoff. Worked on projects, which involved developing timing assertions/constraints for high-speed synchronous interfaces, memory interfaces (DDR2, QDR2), designs with multiple clocks and voltage domains. Experience with industry leading EDA tools from Cadence and Synopsys. Experience leading a project from concept to tape-out and leading a team of engineers. Specialties: Physical Design, Place & Route, Static Timing Analysis (STA), Synthesis, Physical Verification, Python, Tcl

Experience

1. Technical Leader Asic Engineering

   Cisco

   Jan 2017 — Present · San Francisco, CA, US

Education

• Vaagdevi College Of Engineering, Warangal

  B.Tech

  1999 — 2003

• Indian Institute of Technology, Madras

  Master of Technology

  2003 — 2005

Skills

• Logic Synthesis
• Physical Design
• Synopsys Primetime
• P&R
• Ic
• Synopsys Design Compiler
• Rtl Design
• Debugging
• Soc
• Edi
• Asic
• Timing Closure
• Integrated Circuit Design
• Timing
• Eda
• Systemverilog
• Floorplanning
• Functional Verification
• Formal Verification
• Verilog
• Rtl Coding
• Tcl
• Vlsi
• Processors
• Icc
• Primetime
• Logic Design
• Spyglass
• Static Timing Analysis
• Semiconductors