Kranthi Kumar Pulipati
\"Aspiring VLSI Design & verification Engineer | Specialized in Verilog, System Verilog, UVM | Focused on RTL Design and Verification Solutions\"
- Role
- Design Verification Engineer at Vlsi First
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
Experience
Design Verification Engineer
Apr 2024 — Present · Hyderabad, IN
Education
St. Joseph's ITI
NCVT, Electronic Mechanic
2013 — 2015
ZP High School Amudala
High School Diploma
Nuzvid Polytechnic
Diploma of Education, Electrical and Electronics Engineering
2015 — 2019
Nuzvid Polytechnic
Master's Degree, Electrical and Electronics Engineering
Sri Vani School of Engineering, Chevuturu (V), G. Konduru Mandal, Pin- 521230(CC-7J)
Bachelor of Technology, Electrical and Electronics Engineering
2019 — 2022
ZP High School ,Tadepalli
Ssc
2012 — 2013
St. Joseph's Imaging
Bachelor of Industrial Engineering, Electronic Mechanic
Sri Vani Education Centre
Bachelor of Technology, Electrical and Electronics Engineering
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