Kovid Eega

About Kovid Eega

Design Verification Engineer with 4+ years of working experience in the semiconductor industry. Efficiency in Handling VIP\'s without dependency, Skilled in Universal Verification Methodology (UVM), SystemVerilog and Verilog. Strong engineering professional with a Bachelor of Technology - BTech focused in Electronics and Instrumentation Engineering from Kakatiya University.• Hands on experience in creating test cases, coverage report, regression debugging, debugging of verification environment using UVM verification Methodologies. • Worked on UVM/ C based environment for Chip Level Verification. • Experience in developing test plans, test cases in C language and System Verilog • Experienced in Developing and debugging failing test cases in SV/UVM. • Good Knowledge of debugging issues at block level and SOC level. • Good Understanding of Verification Concepts of SystemVerilog and UVM Methodology. • Attended Cadence Design System & Mentor Graphics Online Trainings Sessions on System Design verification Course. • Protocol Knowledge: AMBA-APB, AHB & AXI, SPI and PCIE (basic knowledge) • Tools: Synopsys VCS, Verdi, Cadence (jasper gold) Mentor Graphics (Modelsim), Questasim and Xilinx ISE.

Experience

1. Design Verification Engineer (Cw)

   Altera

   Dec 2024 — Present · Kochi, IN

   PSG_Lucedia_PCOE :* Ethernet AN/LT* Debugging* GUI Testing* UVM methodology* System verilog * Assertions* Constraints* Coverage

Education

• SR college for Boys

  Higher secondary Education, MPC

• Maven Silicon

  Design Verification Intern, Advanced VLSI Design and Verification

• Kakatiya University

  Bachelor of Technology, Electronics

  2019

• SR National High School

  SSC, SSC

• Kakatiya Institute of Technology & Science, Yerragattu Hillocks, Bheemaram, Hasanparthy, Warangal

  Bachelor of Technology - BTech, Electronics and Instrumentation Engineering

  2015 — 2019