Koushik N S
STA Design Engineer at Intel Corporation
- Role
- Sta (Static Timing Analysis) Design Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Koushik N S
Working on complex designs (SOC or Block level) as a STA/Synthesis profile of lower node…
Experience
Sta (Static Timing Analysis) Design Engineer
Sep 2018 — Present · Bengaluru, IN
Education
Kalasalingam university
Bachelor's Degree
2008 — 2012
Manipal university jaipur
Master's Degree
2012 — 2014
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