Koushalya R
Physical Design @Achronix Semiconductor Corporation
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WORK HISTORY
Physical Design @Achronix Semiconductor Corporation
EDUCATION
SJCE Mysore
BE
San José State University
MS, Electrical Engineering
ABOUT KOUSHALYA R
Leading Fill automation engineer to custom layout, PNR and Full Chip integration teams to help layout design completion. Working experience on physical design concepts including -placement and route, physical design completion (Fill), circuit spice simulation, RC Extraction and EMIR analysis.• Knowledge on layout design for circuits in Cadence Xl (LVS and DRC concepts)• Familiar with std cell circuit design on Cadence Virtuoso.• Familiar with Device characterization of cmos circuits.• Good understanding on NAND Flash memory technologies (SLC and MLC architectures). Tools: Cadence virtuoso, Calibre, Synopsys ICV, ICC, PERC, VCS,HSpice and Finesim, Ansys Totem/Redhawk, Star RC, Primetime, Design Compiler, Modelsim, Matlab Simulink.Technologies : tsmc20nm, intel14nm, intel10nmProgramming : Verilog, C++,Perl
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