Kottisa Amruth
RTL Design Engineer || Master\'s in VLSI Design
- Role
- Rtl Design Engineer (Contract) at NXP Semiconductors
- Location
- Bengaluru, IN
- LinkedIn followers
- 500 followers
About Kottisa Amruth
Highly motivated RTL Design Engineer with expertise in IP integration, SoC assembly, RTL…
Experience
Rtl Design Engineer (Contract)
Sep 2024 — Present · Bengaluru, IN
Performed IP integration and SoC assembly using the Magillem IP-XACT flow, enablingefficient management and connectivity of multiple RTL IP blocks.• Generated IP-XACT views for custom RTL blocks and took ownership of AS and RTL viewsfor four IPs.• Automated top-level RTL generation, address map creation, and register map configurationusing Magillem tools.• Performed RTL linting using Synopsys VC Spyglass for LPI2C IP, resolved lint violations andimproved RTL quality compliance.• Performed Clock Domain Crossing (CDC) analysis on SGMII PHY using Siemens QuestaCDC tool and maintained waiver reports for valid CDC exceptions after careful root causeanalysis.• Developed a Python script to auto-generate TCL files for Magillem IP-XACT flow byextracting bus interfaces, address maps, and RTL parameters from IP blocks.• Developed RTL code for digital IP blocks using Verilog.• Participated in architecture and design reviews, incorporating feedback to meet projectstandards and best practices.
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