Kotakuri Ganesh

WORK HISTORY

EDUCATION

ABOUT KOTAKURI GANESH

I am a VLSI Trainee and Design Verification Engineer aspirant with a strong foundation in Digital Electronics and RTL design using Verilog. Currently associated with Technical Hub, Aditya University, where I actively focus on building industry-relevant skills through hands-on practice and continuous learning. My learning journey includes designing and verifying combinational digital circuits, understanding RTL fundamentals, and implementing logic using behavioral and structural modeling in Verilog. I consistently work on strengthening my core concepts and improving my problem-solving ability through practical implementations. I actively share my learning journey on LinkedIn, which has helped me improve my technical clarity, documentation skills, and consistency as an engineer. I am open to entry-level Design Verification / RTL opportunities where I can contribute, learn from experienced professionals, and grow into a skilled VLSI engineer.Core Interests:• Digital Design & RTL• Verilog HDL• Combinational Logic• Design Verification (Basics) Open to internships, fresher roles, and meaningful technical discussions.Email- k••••••••@gmail.com