Koppula Naresh
Asic Digital Design Staff Engineer @ SYNOPSYS
- Role
- Asic Digital Design Staff Engineer at Synopsys Inc
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Koppula Naresh
Senior Design Engineer at SYNOPSYS: Working on M-PHY RMMI G4 where in my contributions include the configuration updates on the RTL using the internal flow and performing the Synth, CDC Formality and add/update the constraints and setups, also support the customer cases with the analysis as on when needed with the complete understanding of the M-PHY clocking and Reset Architecture.Design Engineer at Eximius Design worked on IP Integration of RTL at block level using the magillem IP-XACT standards accounting for the architectural changes in the design cycle, delivering SDC and block IP-XACT to SOC after QC. Also owned up the GPIO RTL generation to ensure the Test signals are connected to the appropriate PAD for the TEST MODE debug.
Experience
Asic Digital Design Staff Engineer
Mar 2024 — Present · Hyderabad, IN
Education
KESHAV MEMORIAL INSTITUTE OF TECHNOLOGY HYDERABAD
Bachelor of Technology (BTech), ELECTRONICS AND INSTRUMENTATION
2009 — 2013
NIT WARANGAL
Master of Technology (MTech), ELECTRONICS AND INSTRUMENTATION
2015 — 2017
Skills
- Microsoft Office
- Matlab
- Microsoft Excel
- Customer Service
- Engineering
- Management
- C
- Automation
- Verilog Hdl
- Perl
- Instrumentation
- Electrical Wiring
- Leadership
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