Karan Shah
- Role
- Asic Design Engineer at Apple
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
About Karan Shah
A seasoned engineer with expertise of full front end flow, including design & …
Experience
Asic Design Engineer
Dec 2020 — Present
Responsible for specifying and/or micro-architecting digital blocks in advanced mixed signal circuits, Writing RTL codes for these blocks, Writing UPF for the power intent of these blocks Performing VCLP, Lint, CDC/RDC checks, Participating in design verification by writing meaningful assertions and debugging code, Supporting lab bring-up by writing test scripts, proposing experiments and so on
Skills
- Perl
- Analog
- Synopsys Design Compiler
- Systemverilog
- Formal Verification
- Algorithms
- Embedded Software
- Microprocessors
- Apb
- Universal Verification Methodology (Uvm)
- Nvme Protocol
- Ni Labview
- C
- Mentor Questasim
- Verilog
- I2c
- Functional Verification
- Debugging
- Synopsys Vcs
- Embedded C
- Functional Coverage
- Digital Electronics
- Asic
- Uvm
- C++
- Application-Specific Integrated Circuits (Asic)
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.