Yasaswi Kamireddy
Design Verification
- Role
- Design Verification Engineer at Apple
- Location
- Santa Clara, CA, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Yasaswi Kamireddy
I am a Design Verification Engineer with an ever growing passion for semiconductor engineering.
Experience
Design Verification Engineer
Feb 2020 — Present · US
Education
University of Illinois Chicago
Master's Degree, Electrical and Computer Engineering
2014 — 2016
Vellore Institute of Technology
Bachelor's Degree, Electronics and Communications Engineering
2010 — 2014
Skills
- Python
- Microsoft Word
- Semiconductors
- Cadence Virtuoso
- Management
- Teamwork
- System Verilog
- Microsoft Excel
- Powerpoint
- Very-Large-Scale Integration (Vlsi)
- Simulink
- Sql
- Linux
- Modelsim
- Windows
- Verilog
- C
- Programming
- Microsoft Office
- Java
- Universal Verification Methodology (Uvm)
- C++
- Research
- Atalanta
- Microcontrollers
- Html
- Vhdl
- Simulations
- Plc Programming
- Perl
- Embedded Systems
- Altera Quartus
- Matlab
- Time Management
- Scada
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