Kishore Yadav A
Lead Physical Design Engineer
- Role
- Senior Technical Lead at HCLTech
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Kishore Yadav A
Working as a Lead Physical Design Engineer.Presently working on 5nm project with Intel.Worked on 6nm and 4nm projects in MediatekWorked for Intel 10nm technology.Worked on all the stages of Place and Route flow from Netlist to GDSII [Including STA/DRC/LVS/IR].Have good hands on experience on tools like Synopsys Fusion Compiler, IC Compiler II and Cadence\'s Innovus for P&R, Prime Time for sign off Timing, Caliber for DRC.Worked on the timing closure of critical blocks which have RP groups and M-BIT registers.Good at timing analysis & debugging the various P&R and PV issues.Having Good knowledge of all the sign-off checks including IR-drop.
Experience
Senior Technical Lead
Jul 2025 — Present · Hyderabad, IN
Education
Jain (Deemed-to-be University)
Master of Business Administration - MBA, system and operations management
Jawaharlal Nehru Technological University
Bachelor's of technology (ECE), Electrical, Electronics and Communications Engineering
2009 — 2013
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