Kishora Naik S
PD/STA Engineer
- Role
- Physical Design Engineer Sta at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Kishora Naik S
With 8 years of hands-on experience in Static Timing Analysis (STA), I have contributed to multiple SoC, IP, and test chip projects, along with subsystem-level timing analysis. My expertise lies in achieving timing closure across complex designs while maintaining accuracy, performance, and design integrity.I am highly proficient in Synopsys PrimeTime and have extensive experience developing automation scripts (Tcl, Perl) to streamline STA flows and enhance productivity. My background includes close collaboration with cross-functional design, synthesis, and P&R teams to deliver high-quality results under challenging project timelines.I’m passionate about exploring new timing methodologies, improving design efficiency, and continuously advancing my technical expertise in STA and digital implementation.
Experience
Physical Design Engineer Sta
May 2024 — Present · Bengaluru, IN
Education
Dayananda Sagar College of Engineering, BANGALORE
Master of Technology - MTech
2015 — 2017
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