Kishan B
Layout Design Engineer
- Role
- Layout Design Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Layout Design Engineer
Nov 2021 — Present · Bengaluru, IN
Education
Visvesvaraya Technological University
Bachelor's degree
2007 — 2011
Skills
- Analog
- Drc
- Asic
- C
- Lvs
- Design Rule Checking (Drc)
- Perl Scripting,Physical Verification Using Caliber,Virtuoso,Pyxis,Ic Station
- Layout Versus Schematic (Lvs)
- Application-Specific Integrated Circuits (Asic)
- Semiconductors
- Cmos
- Verilog
- Soc
- Digital Electronics
- Cadence Virtuoso
- Perl
- Embedded Systems
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