Kirtesh Tiwari

About Kirtesh Tiwari

With over 15 years of experience in VLSI Physical Design, I have had the privilege of working on some of the most advanced semiconductor technologies in the industry—from 3nm and 5nm nodes to legacy nodes like 180nm. My journey has been driven by a passion for solving complex design challenges and delivering optimized solutions that meet stringent performance, power, and area (PPA) requirements.I specialize in the complete Netlist-to-GDSII flow, with deep expertise in: Synthesis, Place & Route, Physical Verification (PV), and Logic Equivalence Check (LEC) Static Timing Analysis (STA), Clock Tree Synthesis (CTS), IR/EM Analysis, and Low-Power Design PV and LEC at both Block and Top Level, including Low-Power LEC Automation and optimization using TCL and Python scripting Exploring Machine Learning applications in Physical DesignThroughout my career, I’ve contributed to multiple tape-outs across cutting-edge nodes like 3nm, 5nm, 7nm, and 10nm, ensuring robust designs for high-performance computing and low-power applications. I thrive in fast-paced environments where innovation and precision go hand in hand.If you’re passionate about semiconductor design, advanced nodes, or automation in VLSI, let’s connect—I’m always excited to share knowledge and explore new ideas.

Experience

1. Staff Engineer

   Qualcomm

   Oct 2022 — Present · Bengaluru, IN

Education

• Dr. A.P.J. Abdul Kalam Technical University (AKTU), Lucknow

  B.Tech, Electrical, Electronics and Communications Engineering

Skills

• Perl
• Eda
• Verilog
• Rtl Coding
• Logic Design
• Vhdl
• Integrated Circuit Design
• Rtl Design
• Application-Specific Integrated Circuits (Asic)
• C
• Physical Verification
• Dft
• Cmos
• Ncsim
• Open Verification Methodology
• Xilinx
• Systemverilog
• Functional Verification
• Routing
• System on a Chip (Soc)
• Drc
• Static Timing Analysis
• Synopsys Tools
• Clock Tree Synthesis
• Physical Design
• Cadence Virtuoso
• Vlsi
• Very-Large-Scale Integration (Vlsi)
• Tcl
• Asic
• Low-Power Design
• Floorplanning
• Layout Versus Schematic (Lvs)
• Logic Synthesis
• Lvs
• Cadence
• Formal Verification
• Soc
• Design Rule Checking (Drc)
• Modelsim