Kiratey Patil

SoC Design Engineer at Intel Corporation

Role
Soc Design Engineer at Intel
Location
Bengaluru, KA, IN
LinkedIn followers
500 followers

About Kiratey Patil

I am skilled in Verilog HDL, System Verilog and have a good hand in Data Structures using ‘C’. Design/Verify/Test LeWiz’s Three Ethernet MAC IP Cores (LMAC) each supporting different speed modes. CORE3: 100G/50G/40G/25G/10G, CORE2: 10G/5G/2.5G/1G, and CORE1: 1G/100M/10M. Implemented LMAC-CORE1 on Xilinx\'s ZCU102 UltraScale+ FPGA Board and tested it by running several network operations like PING, TELNET, WGET, Remote Desktop Login, etc. after populating the LMAC with packets. Worked on an already available RISC-V processor to make it a fault-tolerant system (single and multi-core). Worked on an already available WiFi project to add safety features so that it can create a wireless network that can only be located and connected by authorized client devices while other commercial devices such as laptop computers, phones, etc. cannot locate or interfere with this private wireless network.

Experience

  1. Soc Design Engineer

    Intel

    Jun 2023 — Present · Bengaluru, IN

    Oversee definition, design, verification, and documentation for SoC (System on a Chip) development. Determine architecture design, logic design, and system simulation. Define module interfaces/formats for simulation. Perform Logic design for integration of cell libraries, functional units and sub-systems into SoC full chip designs, Register Transfer Level coding, and simulation for SoCs. Perform all aspects of the SoC design flow from high-level design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing.

Education

  • Campbellsville University

    Professional MBA

  • Navjeevan Dnyanpeeth English Medium School, Pusad

    Secondary School, Academic

    2007 — 2008

  • Dr. N. P. Hirani Institute of Polytechnic, Pusad

    Diploma in Engineering, Electronics and Telecommunication Engineering

  • San José State University

    Master’s Degree, Electrical Engineering

  • Sinhgad College of Engineering

    Bachelor of Engineering (B.E.), Electronics and Telecommunication Engineering

Skills

  • Embedded C
  • Engineering
  • Matlab
  • Windows
  • Very-Large-Scale Integration (Vlsi)
  • Python
  • Universal Verification Methodology (Uvm)
  • Unix
  • Application-Specific Integrated Circuits (Asic)
  • C
  • Programming
  • Asic
  • Vhdl
  • Synopsis
  • Leadership
  • Assembly Language
  • Electronics Hardware Design
  • Verilog
  • Powerpoint
  • Microsoft Excel
  • Electrical Engineering
  • Embedded Systems
  • Microsoft Office
  • Vlsi
  • Microsoft Word
  • Electronics
  • System Verilog

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Kiratey Patil — Soc Design Engineer at Intel in Bengaluru, KA, IN | Unifers