Kiran T R

About Kiran T R

Physical Design Engineer specializing in advanced-node RTL2GDS implementation across Intel 18A, TSMC 5nm/7nm, Samsung 4nm, and Intel 10nm. I focus on block and subsystem ownership: floorplanning, timing closure, clocking, IO ring design, port architecture, ECO execution, and PPA-driven experiments. Delivered clean convergence on multi-million-gate partitions and contributed to several high-visibility IPs, earning multiple Intel recognition awards. I enjoy solving tough design bottlenecks, refining methodologies, and driving silicon to stable, signoff-clean completion.Outside silicon, I explore the world through a camera. I co-founded Mysore Photowalk and led multiple walks across Mysore, documenting historic architecture and lesser-known corners of the city. Architectural photography remains my way of observing structure, symmetry, and design.

Experience

1. Cpu Physical Design Engineer

   Intel

   Jun 2025 — Present · Bengaluru, IN

Education

• Vidyavardhaka College of Engineering

  Bachelor of Engineering (B.E.), Electrical and Electronics Engineering

  2006 — 2011

• WIPO-UNIGE Summer School on Intellectual Property

  DL101, Intellectual Property

  2009 — 2009

• Sri Jayachamarajendra College Of Engineering

  Master of Technology (M.Tech.), VLSI Design & Embedded Systems

  2012 — 2014

Skills

• Fpga
• Tanner Eda
• C
• Programming
• Microsoft Office
• Vlsi
• Vhdl
• Semiconductors
• Msp430
• Matlab
• Arm
• C++
• Very-Large-Scale Integration (Vlsi)
• Simulink
• Microcontrollers
• Verilog
• Pspice
• Embedded Systems
• Eda
• Labview
• Eagle Pcb
• Iar Embedded Workbench
• Starrc
• Synopsys Tools
• Backend Design
• Physical Design
• Synopsys Primetime
• Autocad
• Digital Signal Processors
• Tcl
• Xilinx
• Shell Scripting
• Cadence
• Cadence Virtuoso
• Digital Circuit Design
• Modelsim
• Electronics
• Integrated Circuit Design
• Xilinx Ise
• Spice