Kiran T.

WORK HISTORY

EDUCATION

ABOUT KIRAN T.

I am a passionate front-end RTL Design and Verification engineer with 15+ years of deep experience in IP and SoC functional verification, formal verification, and methodology development. My work focuses on architecting high-quality verification environments, enabling first-silicon success, and increasingly, leveraging AI agents to accelerate verification workflows, debug insights, and simulation efficiency.Over the years, I have built and led verification solutions across complex, high-performance IPs and SoCs in domains such as PCIe, USB, HSIC, SSIC, clock generation, power control, and multi-domain subsystem interactions. I specialize in developing scalable SystemVerilog/UVM verification environments, formal verification strategies, and Python-driven automation that strengthens coverage, reduces debug time, and improves verification predictability.I am particularly passionate about the future of AI-augmented design verification. I am actively building AI agents that analyze logs, identify failure patterns, recommend test actions, automate infrastructure tasks, and enhance verification productivity.Core Competencies:Front-End Functional RTL Design & VerificationFormal Verification: JasperGold, Questa Formal, OneSpinIP & SoC Verification Expertise: • PCIe, USB, HSIC, SSIC • Clocking, Reset, Power & FSM Verification (ABV) • Low-power test development and SoC-level power concepts • Firmware co-simulation and HW-SW verificationVerification Methodology & Architecture: • SystemVerilog, UVM based environments • Verification planning, coverage strategy, and closure • Python-based verification tooling and AI-driven automation • Debug experience with Synopsys VCS, Cadence Xcelium, Mentor QuestaProgramming & Scripting:VHDL, Verilog, SystemVerilog, UVM, Specman, C, Perl, Shell, PythonVersion Control:ClearCase, Git, SVNWhat Drives Me: Building intelligent, scalable, and automation-rich verification ecosystems that reduce cycle time, enhance observability, and empower teams to verify increasingly complex SoCs with confidence. I believe the next leap in semiconductor verification will be powered by AI agents, and I’m excited to be contributing to that evolution.