Kiran Patil
VLSI Lead with FPGA and ASIC expertise
- Role
- Vlsi Lead at Wipro
- Location
- Pune, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Kiran Patil
10 years of experience in FPGA and ASIC Design. • 5.5 years of experience in FPGA…
Experience
Vlsi Lead
Jul 2022 — Present · Pune, IN
Education
North Maharashtra University
Bachelor of Engineering (B.E.)
2008 — 2012
Maharashtra State Board
10th
2005 — 2006
Shivaji University
Master of Technology (M.Tech.)
2013 — 2015
Sandeepani School of VLSI Design
Diploma
2012 — 2013
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