Kiran N
SoC Design Engineer
- Role
- Soc Design Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Kiran N
Physical Design and Static Timing Analysis knowledge.*Worked on Place and Route and Timing closure tools.*Schematic and Layout Design Automation.*Worked on various flow development projects.
Experience
Soc Design Engineer
Oct 2019 — Present · Bengaluru, IN
Education
St.Joseph Engineering College,Vamanjoor
Bachelor of Engineering (B.E.)
2011 — 2015
BITS Pilani Work Integrated Learning Programmes
Master of Technology - MTech
2020 — 2021
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