Kiran Mallavarjula
Senior Technical Manager at silicon patterns
- Role
- Senior Technical Manager at Silicon Patterns
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Kiran Mallavarjula
Experienced IC Design Engineer with 14 years of expertise across all stages of physical design, including floorplanning, power planning, clock tree synthesis (CTS), placement and routing, parasitic extraction, timing analysis, signal integrity analysis and repair, engineering change order (ECO) implementation, static and dynamic voltage drop (IR) analysis, and physical verification.Currently working on advanced technology node designs (5nm and 3nm), collaborating with various customers to develop and implement efficient flows and methodologies for placement, CTS, and routing to meet stringent performance, area, and power goals.Proven track record of resolving critical design challenges and enabling successful project execution. Adept at providing technical support and in-depth training to help customers achieve optimal design outcomes.Core Competencies:Advanced Node Physical Design (5nm/3nm)Floorplanning & Power PlanningCTS & Place and RouteTiming Closure & Signal IntegrityStatic/Dynamic IR Drop AnalysisPhysical Verification (DRC/LVS)Design ECOsFlow & Methodology DevelopmentCustomer Support & Training
Experience
Senior Technical Manager
May 2025 — Present · Bengaluru, IN
Education
Indira Gandhi National Open University
Diploma in management, Management
Vidhya Jyothi Highschool
SSC
2002 — 2004
VEDA INSTITUTE OF INFORMATION TECHNOLOGY PRIVATE LIMITED
Diploma in Physical Design , VLSI
Gurukrupa junior college
Intermediate, M.P.C
Jawaharlal Nehru Technological University Hyderabad (JNTUH)
Engineer's Degree, Electrical, Electronics and Communications Engineering
2006 — 2010
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