Kiran Kumar Jallada

About Kiran Kumar Jallada

Experience in ASIC Design Verification of multiple SOCs and Processors. I\'ve enjoyed…

Experience

1. Smts

   AMD

   May 2021 — Present · Hyderabad, IN

   DFX- Design for Debug(DFD) & DFT JTAG STAC SOC VerificationRoles and Responsibilities: SOC DFD DV Lead Good understanding of SOC level DFD & DFT JTAG STAC Routers verification. Basic understanding of DFD blocks – debug bus, IpTrigActions, CrossTrigger Lowpower scenarios - PG S3 S5, TCB, Realboot, HDT, BumpPins, Security, Multi-Die. In Mendocino, Phoenix2, Strix Halo and Magnus projects, Worked on porting andbringups passrate as per Milestones with Functional and Interface Toggle coverage. Worked on local Test runs and Debugged the Regressions failures of tests.

Education

• GIOE (Government Institute Of Electronics)

  Special Diploma

  2003 — 2006

• Jawaharlal Nehru Technological University

  Bachelor of Technology (B.Tech.)(CCC)

  2008 — 2012

• Jawaharlal Nehru Technological University

  Master of Technology (M.Tech.)

  2012 — 2014

• SSSVN

  SSC

Skills

• Fpga
• Logic Design
• Asic
• Specman
• Verilog
• Low-Power Design
• Open Verification Methodology
• Processors
• Logic Synthesis
• Uvm
• Primetime
• Ncsim
• Soc
• Eda
• Static Timing Analysis
• Rtl Design
• Amba Ahb
• Timing Closure
• Formal Verification
• Vlsi
• Application-Specific Integrated Circuits (Asic)
• Modelsim
• Tcl
• Rtl Coding
• Functional Verification
• Xilinx
• Systemverilog
• Field-Programmable Gate Arrays (Fpga)