Kiran Jambhale
Staff Engineer @Samsung Semiconductor
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WORK HISTORY
Staff Engineer @Samsung Semiconductor
Bengaluru, IN
EDUCATION
Finolex Academy of Management & Technology
Bachelor of Engineering - BE, Electrical and Electronics Engineering
Paisa Fund English School and Junior College , Sangameshwar
SSC
Birla Institute of Technology and Science, Pilani
Master of Technology - MTech, Microelectronics
Paisa Fund English School and Junior College , Sangameshwar
HSC
ABOUT KIRAN JAMBHALE
Over 8.5 years of experience in high-performance digital system development, I am experienced RTL Design Engineer specializing in the following:RTL Micro-architecture & Design: Expert in SystemVerilog/Verilog for ASIC/SoC and FPGA, specializing in high-speed pipeline architectures and complex digital logic.PPA Optimization: Proven track record of delivering optimized designs by meeting rigorous Power, Performance, and Area constraints through low-power techniques and Static Timing Analysis (STA).Protocol & Interface Expertise: Proficiency in AXI-4 (Full/Lite/Stream), APB, Ethernet/EtherCAT, DDR3, and high-speed SerDes (Wizard Link), alongside various serial and display interfaces.End-to-End Execution: Comprehensive experience across the full ASIC/FPGA design cycle, including CDC/RDC analysis, linting, synthesis, and post-silicon bring-up/root-cause analysis.Tool & Domain Mastery: Skilled in Synopsys DC, Spyglass, Vivado, and Quartus with automation via TCL scripting, applied across ISP, DSP (RADAR), and industrial automation domains.
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