Kimiya Bunger
- Role
- Soc Hardware Engineer at Intel
- Location
- San Mateo, CA, US
- LinkedIn followers
- 500 followers
About Kimiya Bunger
I’m an experienced Design Verification Engineer with a pedigree from Berkeley’s renowned…
Experience
Soc Hardware Engineer
Aug 2019 — Present
Work on developing testbench infrastructure for power management components for Intel\'s Xeon server SoC\'s using OVM (ex: Drivers/Monitors/Scoreboards)-Developed detailed testplans for functional verification -Worked on coding functional coverage as well as SVA
Skills
- Low-Power Design
- Computer Architecture
- C++
- Power Management
- Cadence Virtuoso
- Vcs
- Analog
- Functional Verification
- Integrated Circuit Design
- Semiconductors
- Formal Verification
- Perl
- Dve/Verdi
- Signal Processing
- Veritas Cluster Server
- Electrical Engineering
- Ic
- Testing
- Fpga
- Integrated Circuits (Ic)
- Functional Coverage
- Python
- Algorithms
- Unix
- Uvm
- Sva
- Simulations
- Systemverilog
- Ovm
- Verilog
- Field-Programmable Gate Arrays (Fpga)
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